1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a process of planarizing an insulating interlayer deposited on a lower pattern layer in a semiconductor device.
2. Discussion of the Related Art
In manufacturing highly integrated semiconductor devices, including device processes for miniaturization (i.e., lower design rules) and increasing capacitances, the formation of multiple layers within a limited area increases the complexity of the structure of the devices, thereby causing additional surface unevenness and increasing the need for planarization. Planarization is a process in which a step differential is removed or reduced by planarizing one or more intermediate layers. For example, a first portion of an insulating interlayer, for example, a metal wiring layer, may be at a higher level than a second portion of the insulating interlayer, for example, the gaps between the lines of metal. As a result, the surface of the insulating interlayer should be planarized by, for example, chemical-mechanical polishing. Chemical-mechanical polishing is a process that may obtain remove any unevenness over relatively large areas. In planarization by chemical-mechanical polishing, the uneven layer is planarized by a frictional force between a slurry, functioning as the chemical polishing material, and a pad, functioning as the mechanical polishing material. Chemical-mechanical polishing generally uses a surfactant, for example, TK, having a predetermined flow rate (“flux”) typically expressed as the amount of supplied surfactant in milliliters flowing over the surface per minute.
FIG. 1 shows the result of a conventional process for chemical-mechanical polishing. An insulating interlayer 102 is deposited on a substrate 106, on which a metal wiring layer (not shown) has been formed, and a contact hole 104 is etched to form a contact plug (not shown) in the planarized surface of the insulating interlayer. Although the desired thickness of the majority of the insulating interlayer 102 is 750 nm after planarization, the insulating interlayer thickness is 357 nm after planarization, or about 300 nm less than the desired thickness, and is achieved by polishing the insulating interlayer for about 100 seconds at a TK flux of 6.5 ml per minute. The conventional process for chemical-mechanical polishing is performed as a single-step process at a given flow rate of the surfactant, i.e., a process using a constant TK flux value. The rate of polishing performed with respect to an insulating interlayer deposited on a predetermined pattern may vary according to the specific portions of different surface areas of the insulating interlayer, causing an unevenness throughout the insulating interlayer by imparting a higher-density portion with a thickness different than that of a lower-density portion. This thickness variation can be detected by photographing the planarized layer to observe a color variation across a plan view of the substrate. Different colors can indicate the respectively varying thicknesses of the layer.
With the above-described non-uniformity in the thickness of an insulating interlayer, the depth of focus in a photolithography step increases, thereby degrading tolerance margins. Moreover, the inconsistent size of the cross section of the insulating interlayer results in difficulties in performing a contact etching process (contact plug formation) with respect to the insulating interlayer. As a result, the number of defective contacts generated increases, which leads to more open/short failures and higher leakage currents, thereby lowering yield.
As an example, a sample set of eight-inch wafers can be treated with the conventional polishing process, and open/short failure testing is performed at several hundred positions in each wafer, followed by leakage current (Icc3) testing. The open/short failure rate has been found to be 4.69%, with an Icc3 failure rate of 57.45%, such that the overall pass rate of only 17.04%.